1. Field of the Invention
The present invention relates generally to a method of forming metal wiring in a semiconductor device. More particularly, the present invention relates to a method of forming metal wiring in a semiconductor device using a dual damascene process in which a trench is formed prior to a via-hole.
A claim of priority is made to Korean Patent Application No. 2003-87414, filed on Dec. 4, 2003, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
Due to the current level of integration in modern semiconductor devices, metal wiring layer having a multi-layer structure has become an important part of many semiconductor devices. As the degree of integration in semiconductor devices continues to increase, the space between the layers in the multi-layer wiring structure decreases accordingly. As a result, parasitic resistance and parasitic capacitance between horizontally and vertically adjacent wiring layers increases, thereby causing an increasingly significant impact on the performance of many semiconductor devices.
Increasing parasitic resistance and capacitance in a semiconductor device typically decreases the device's performance by causing signal delays, increasing power consumption, and increasing leakage current. Accordingly, a modern semiconductor device having a multi-layer wiring structure with small parasitic resistance and capacitance is desired.
Parasitic resistance and capacitance are typically minimized in a multi-layer wiring structure where the wiring is formed from a metal having a low specific resistance and where an insulating layer formed from a dielectric material having a low dielectric constant is used. Intensive research has been conducted on the use of copper as a low specific resistance material for use in the formation of metal wiring.
Where copper is used as a metal wiring material, the resulting wiring pattern is generally formed not by a photolithography process, but rather by a dual damascene process. FIGS. 1A through 1F are cross sectional views illustrating the formation of metal wiring in a semiconductor device according to a conventional dual damascene process.
Referring to FIG. 1A, a conductive layer 20 is formed on a semiconductor substrate 10 and a first stopping layer 30 is formed on conductive layer 20. An insulating interlayer 40 is formed on first stopping layer 30 and a second stopping layer 50 is formed on insulating interlayer 40.
Referring to FIG. 1B, a first photoresist pattern 60 is formed on second stopping layer 50.
First photoresist pattern 60 comprises first and second openings 70a and 70b, which partially expose second stopping layer 50. First opening 70a is wider than second opening 70b. Accordingly, first opening 70a forms a relatively large via-hole and second opening 70b forms a relatively small via-hole.
Referring to FIG. 1C, second stopping layer 50 and insulating interlayer 40 are partially etched using first photoresist pattern 60 as an etching mask to form a third opening 80a having a first width W1 and a fourth opening 80b having a second width W2. Third and fourth openings 80a and 80b form via-holes partially exposing first stopping layer 30. Following the formation of third and fourth openings 80a and 80b, first photoresist pattern 60 is completely removed. After being partially etched, second stopping layer 50 and insulating interlayer 40 are referred to as second stopping layer 50a and insulating interlayer 40a, respectively.
Referring to FIG. 1D, a mask layer 90 filling third and fourth openings 80a and 80b is formed on second stopping layer 50a and an anti-reflection layer 100 is formed on mask layer 90 to prevent reflection from the mask layer in a subsequent photolithography process. Mask layer 90 prevents a focus failure from occurring in the subsequent photolithography process. In the absence of a mask layer, the focus failure generally occurs during an exposing process of the subsequent photolithography process where light fails to properly focus due to a large width of a pattern formed in a device being etched. For example, a focus failure could occur due to a width of a trench corresponding to first opening 70a formed in photoresist pattern 60.
Referring to FIG. 1E, a second photoresist pattern 110 used to form a trench is formed on anti-reflection layer 100. Second photoresist pattern 110 includes a fifth opening 120a and a sixth opening 120b, which partially expose anti-reflection layer 100. A width of a trench corresponding to fifth opening 120a is greater than first width W1 and a width of a trench corresponding to sixth opening 120b is greater than second width W2 of fourth opening 80b. 
Photoresist pattern 110 is formed by first forming a photoresist film (not shown) on anti-reflection layer 100 and then exposing and developing the photoresist film.
Referring to FIG. 1F, anti-reflection layer 100, mask layer 90, second stopping layer 50a, and insulating interlayer 40a are successively etched using second photoresist pattern 110 as an etching mask. Then, mask layer 90, second photoresist pattern 110 and anti-reflection layer 100 are completely removed. After second stopping layer 50a and insulating interlayer 40a are etched, they are referred to as second stopping layer 50b and insulating interlayer 40b. 
The foregoing etching and removing processes form third and fourth openings 80a and 80b, which partially expose first stopping layer 30. The etching and removing processes further form seventh and eighth openings 130a and 130b connected to third and fourth openings 80a and 80b, respectively. Seventh opening 130a has a third width W3, which is larger than first width W1, and eighth opening 130b has a fourth width W4, which is larger than second width W2.
Third and fourth openings 80a and 80b function as via-holes and seventh and eighth openings 130a and 130b function as trenches in a metal wiring of a semiconductor device.
FIG. 2 is a cross-sectional view illustrating some problems that typically arise in the conventional dual damascene process.
Referring to FIG. 2, problems arise in the conventional dual damascene process during the etching process using second photoresist pattern 110 as an etching mask and also during the process of removing second photoresist pattern 110 and mask layer 90.
A first problem arises where third opening 80a has a sufficiently large width, as, for example, in a pad region. A portion of first stopping layer 30 is etched away, thus partially exposing conductive layer 20 as shown at a portion “A” in FIG. 2.
A second problem arises where a stepped portion at the interface of third and fourth openings 80a and 80b and trenches 130a and 130b respectively, is formed to be round, as shown at portion “B” in FIG. 2.
A third problem arises where insulating interlayer 40b is partially removed under second stopping layer 50b between insulating interlayer 40b and second stopping layer 50b, as shown at portion “C” in FIG. 2. The partial removal of insulating interlayer 40b under second stopping layer 50b is called an undercut phenomenon.
A fourth problem arises where second stopping layer 50b becomes narrow between seventh and eighth openings 130a and 130b, as shown at a portion “D” in FIG. 2.
The problems described above alter the electrical characteristics of the semiconductor device and often cause metal wiring failures, thereby reducing the reliability of the semiconductor device.
A dual damascene process is disclosed, for example, in U.S. Pat. No. 6,589,711. U.S. Pat. No. 6,589,711 discloses a dual damascene process using a bi-layered mask layer in which a metal wiring pattern is formed using an imaging layer and a bottom anti-reflection coating (BARC).
Because of the problems arising in the conventional dual damascene process, an improved method of forming a metal wiring is desired.